Display pixel, display apparatus having an image pixel and method of manufacturing display device

ABSTRACT

In a pixel for displays capable of simplifying manufacturing process, a display apparatus having a simplified pixel structure and a method of manufacturing a cost competitive display device, a display pixel includes a channel layer, first to third signal lines, first and second insulating layers and a pixel electrode. The first signal line is formed on the first insulating layer. The first insulating layer insulates the channel layer from the first signal line. The second insulating layer insulates the first signal line from the second and third signal lines, and includes contact holes. The second and third signal lines are connected to the channel layer through the contact holes. The pixel electrode including indium zinc oxide is formed on the identical layer with the first and second signal lines, and disposed on the second insulating layer. Therefore, manufacturing process is simplified and manufacturing time is reduced.

TECHNICAL FIELD

The present disclosure relates to a display pixel, a display apparatushaving an image pixel and method of manufacturing display devices. Moreparticularly, the present disclosure relates to simplifying amanufacturing process of display devices, a display apparatus havingimage pixels and a method of manufacturing display devices.

BACKGROUND

A conventional LCD apparatus includes a plurality of pixel electrodes ora common electrode. The pixel electrodes are generally arranged in amatrix shape and disposed on a first transparent substrate. The commonelectrode corresponding to the pixel electrodes is disposed on a secondtransparent substrate.

A reference voltage is supplied to the common electrode. A pixelvoltage, in accordance with an image signal, is supplied to the pixelelectrodes using thin film transistors (TFTs).

FIG. 1 is a cross-sectional view showing a conventional TFT.

Referring to FIG. 1, the TFT 10 includes a gate electrode 1, a firstinsulating layer 2, a channel layer 3, a source electrode 4, a secondinsulating layer 6 and a drain electrode 5 connected to a pixelelectrode 8.

The gate electrode 1 is formed on a transparent or a proper substrate 9,such as glass, plastic, silicon wafer, steel or others. A gate line (notshown) applying a driving signal to the gate electrode is connected tothe gate electrode.

The first insulating layer 2 is formed over the substrate so as toinsulate the gate electrode 1 and a gate line.

The channel layer 3 corresponding to the gate electrode 1 is formed onthe first insulating layer 2. The channel layer 3 includes an amorphoussilicon channel layer 3 a and N⁺ amorphous silicon channel layer 3 b.

The N⁺ amorphous silicon layer 3 b has first and second pieces separatedfrom each other, and the second piece is formed on the amorphous siliconlayer 3 a.

The source electrode 4 is connected to the first piece of the N⁺amorphous silicon channel layer 3 b, and the drain electrode 5 isconnected to the second piece of the N⁺ amorphous silicon channel layer3 b.

The second insulating layer 6 is formed over the transparent substrate9, and disposed on the source electrode 4 and the drain electrode 5. Thesecond insulating layer 6 includes a contact hole 6 a through which thedrain electrode 5 is partially exposed.

The pixel electrode 8 is formed on the second insulating layer 6, andconnected to the drain electrode 5 through the contact hole 6 a.

The second insulating layer 6 includes the contact hole 6 a disposedbetween the drain electrode 5 and the pixel electrode 8. Therefore, moresteps of manufacturing the TFT 10 having a complex structure are added.

DISCLOSURE OF THE INVENTION

The present invention provides a display pixel capable of simplifyingmanufacturing process.

The present invention also provides a method suitable for manufacturinga simplified display pixel.

The present invention also provides a display apparatus having asimplified display image pixel.

The present invention also provides a method suitable for manufacturingthe above display apparatus.

Display pixels in accordance with an exemplary embodiment of the presentinvention include a channel layer, a first signal line, an insulatinginterlayer, a second signal line, a third signal line and a pixelelectrode. The channel layer includes a channel that may be formed byapplying a first voltage, and the channel transports an electron. Thefirst signal line supplies the first voltage to the channel layer. Theinsulating interlayer insulates the first signal line from the channellayer, and includes a first contact hole and a second contact holethrough which the channel layer is partially exposed. The second signalline is disposed on the insulating interlayer, and electricallyconnected to the channel layer through the first contact hole so as toapply a second voltage to the channel layer. The third signal line isdisposed on the insulating interlayer, and electrically connected to thechannel layer through the second contact hole so as to output the secondvoltage from the channel layer. The pixel electrode is disposed on theinsulating interlayer, and electrically connected to the third signalline.

The method of manufacturing display pixels in accordance with anexemplary embodiment of the present invention is provided as follows. Achannel layer is formed on a transparent or a proper substrate, such asglass, plastic, metal, silicon wafer or others, using a first patternmask. The channel layer has a channel that may be formed by applying afirst voltage. A first signal line applying the first voltage to thechannel layer is formed using a second pattern mask. A first contacthole and a second contact hole are formed on an insulating interlayerusing a third pattern mask. The channel layer is partially exposedthrough the first and second contact holes, and the insulatinginterlayer insulates the first signal line from the channel layer. Asecond signal line electrically connected to the channel layer throughthe first contact hole and a third signal line electrically connected tothe channel layer through the second contact hole are formed on theinsulating interlayer using a fourth pattern mask. A pixel electrodeelectrically connected to the third signal line is formed on theinsulating interlayer.

The display apparatus in accordance with another exemplary embodiment ofthe present invention includes a first substrate, a second substrate anda liquid crystal layer between the first and second substrates.

The first substrate has a first transparent or non transparentsubstrate, a channel layer, a first signal line, a second signal line, athird signal line, a pixel electrode and an etch stop layer. The channellayer is formed on the first transparent substrate. The first signalline having a first electrode insulated from the channel layer isdisposed at a position corresponding to the channel layer. The firstsignal line is extended in a first direction. The second signal line hasa second electrode connected to the channel layer. The second signalline is extended in a second direction. The third signal line having athird electrode connected to the channel is insulated from the secondsignal line. The pixel electrode is formed over the third signal line soas to transmit light supplied through the first transparent substrate orto reflect light from the substrate. The etch stop layer is disposedover the second signal line so as to prevent the second signal line frombeing etched while the pixel electrode is patterned.

The second substrate includes a second transparent substratecorresponding to the first transparent substrate, and a common electrodeformed on the second transparent substrate. The liquid crystal layer isdisposed between the first and second substrates.

The LCD apparatus in accordance with an aspect of the present inventionincludes a first substrate, a second substrate and a liquid crystallayer between the first and second substrates.

The first substrate includes a first transparent or non-transparentsubstrate such as glass, metal, reflective metal, silicon wafer or otherproper materials, a channel layer, a first signal line, a secondelectrode, a second signal line and a pixel electrode. The channel layeris formed on the first transparent substrate. The first signal line,having a first electrode insulated from the channel layer, is disposedat a position corresponding to the channel layer. The second electrodeis connected to the channel layer. The second signal line is disposedover the second electrode. The pixel electrode connected to the channellayer is insulated from the second electrode.

The second substrate includes a second transparent substratecorresponding to the first transparent substrate and a common electrodeformed on the second transparent substrate and corresponding to thepixel electrode. The liquid crystal layer is disposed between the firstand second substrates.

The LCD apparatus in accordance with another aspect of the presentinvention includes a first substrate, a second substrate and a liquidcrystal layer between the first and second substrates.

The first substrate includes a first transparent substrate, a channellayer, a first signal line, a second electrode, a second signal line anda pixel electrode. The channel layer is formed on the first transparentsubstrate. The first signal line having a first electrode insulated fromthe channel layer is disposed at a position corresponding to the channellayer. The second electrode is connected to the channel layer. Thesecond signal line is disposed over the second electrode. The pixelelectrode connected to the channel layer is insulated from the secondelectrode.

The second substrate includes a second transparent substratecorresponding to the first transparent substrate and a common electrodeformed on the second transparent substrate and corresponding to thepixel electrode. The liquid crystal layer is disposed between the firstand second substrates.

The LCD apparatus in accordance with still another aspect of the presentinvention includes a first substrate, a second substrate and a liquidcrystal layer between the first and second substrates.

The first substrate includes a first transparent substrate, a channellayer, a first signal line, an insulating interlayer, a pixel electrode,a second signal line, a third electrode and a third signal line. Thechannel layer is formed on the first transparent substrate. The firstsignal line having a first electrode insulated from the channel layer isdisposed at a position corresponding to the channel layer. Theinsulating interlayer having a plurality of contact holes insulates thefirst signal line from the channel layer. The pixel electrode is formedon the insulating interlayer. The second signal line includes a secondelectrode connected to the channel layer. The third electrode, connectedto the channel layer, is insulated from the second signal line. Thethird signal line disposed on the pixel electrode is electricallyconnected to the pixel electrode.

The second substrate includes a second transparent substratecorresponding to the first transparent substrate and a common electrodeformed on the second transparent substrate and corresponding to thepixel electrode. The liquid crystal layer is disposed between the firstand second substrates.

The method of manufacturing the LCD apparatus in accordance with oneaspect of the present invention is provided as follows.

A first substrate is formed by forming a channel layer, forming a firstsignal line, forming a second signal line, forming a third signal line,forming a pixel electrode and an etch stop layer. The channel layer isformed on a first transparent substrate. The first signal line having afirst electrode insulated from the channel layer is disposed at aposition corresponding to the channel. The second signal line has asecond electrode connected to the channel layer. The third signal linehaving a third electrode insulated from the second signal line isconnected to the channel layer. The pixel electrode is formed over thethird signal line so as to transmit light from the first transparent.The etch stop layer is disposed over the second signal line so as toprevent the second signal line from being etched during patterning thepixel electrode.

A common electrode is formed on a second transparent substratecorresponding to the first transparent substrate to form a secondsubstrate. Liquid crystal is injected into a space between the pixelelectrode of the first substrate and the common electrode of the secondsubstrate.

The method of manufacturing an LCD apparatus in accordance with anotheraspect of the present invention is provided as follows.

A first substrate is formed by forming a channel layer, forming a firstsignal line, forming a second electrode and a pixel electrode andforming a second signal line. The channel layer is formed on a firsttransparent substrate. The first signal line has a first electrodeinsulated from the channel layer and disposed at a positioncorresponding to the channel layer. The second electrode is connected tothe channel layer. The pixel electrode connected to the channel layer isinsulated from the second electrode. The second signal line is formedover the second electrode.

A second substrate is formed by forming a common electrode correspondingto the pixel electrode on a second transparent substrate correspondingto the first transparent substrate. Liquid crystal is injected into aspace between the first and second substrates.

The method of manufacturing an LCD apparatus in accordance with stillanother aspect of the present invention is provided as follows.

A first substrate is formed by forming a channel layer, forming a firstsignal line, forming an insulating interlayer, forming a pixel electrodeand forming a second signal line and a third signal line. The channellayer is formed on a first transparent substrate. The first signal lineincluding a first electrode insulated from the channel layer is disposedat a position corresponding to the channel layer. The insulatinginterlayer including a plurality of openings insulates the first signalline from the channel layer. The pixel electrode is formed on theinsulating interlayer. The second signal line includes a secondelectrode connected to the channel layer. The third signal lineinsulated from the second signal line includes a third electrodeconnected to the channel layer and the pixel electrode.

A second substrate is formed by forming a common electrode correspondingto the pixel electrode on a second transparent substrate correspondingto the first transparent substrate.

Liquid crystal is injected into a space between the first and secondsubstrates.

Therefore, the structure of the display pixel for the LCD apparatus andmanufacturing process are simplified to reduce manufacturing cost andtime.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages of the present invention will becomereadily apparent by reference to the following detailed description whenconsidered in conjunction with the accompanying drawings wherein:

FIG. 1 is a cross-sectional view showing a conventional TFT;

FIG. 2 is a plan view showing a display pixel according to an exemplaryembodiment of the present invention;

FIG. 3 is a cross-sectional view showing A-A′ line of FIG. 2;

FIG. 4 is a plan view showing a channel layer formed on a transparentsubstrate according to another exemplary embodiment of the presentinvention;

FIG. 5 is a cross-sectional view showing B-B′ line of FIG. 4;

FIG. 6 is a plan view showing a lightly doped drain (LDD) structure anda first signal line disposed corresponding to a channel layer accordingto an exemplary embodiment of the present invention;

FIG. 7 is a cross-sectional view showing C-C′ line of FIG. 6;

FIG. 8 is a cross-sectional view showing a channel layer implanted withimpurities at a high concentration according to an exemplary embodimentof the present invention;

FIG. 9 is a cross-sectional view showing a channel layer implanted withimpurities at a low concentration according to an exemplary embodimentof the present invention;

FIG. 10 is a plan view showing contact holes formed corresponding tofirst and second regions according to an exemplary embodiment of thepresent invention;

FIG. 11 is a cross-sectional view showing D-D′ line of FIG. 10;

FIG. 12 is a plan view showing second and third signal line according toan exemplary embodiment;

FIG. 13 is a cross-sectional view showing E-E′ line of FIG. 12;

FIG. 14 is a cross-sectional view showing a display apparatus accordingto another exemplary embodiment of the present invention;

FIG. 15 is a plan view showing a channel region formed on a firsttransparent substrate according to another exemplary embodiment;

FIG. 16 is a cross-sectional view showing F-F′ line of FIG. 15;

FIG. 17 is a plan view showing a lightly doped drain (LDD) structure anda first signal line formed corresponding to a channel layer according toanother exemplary embodiment of the present invention;

FIG. 18 is a cross-sectional view showing G-G′ line of FIG. 17;

FIG. 19 is a plan view showing a contact hole formed in first and secondregions according to another exemplary embodiment of the presentinvention;

FIG. 20 is a cross-sectional view showing H-H′ line of FIG. 19;

FIG. 21 is a plan view showing a second and third signal line accordingto another exemplary embodiment of the present invention;

FIG. 22 is a cross-sectional view showing I-I′ line of FIG. 21;

FIG. 23 is a plan view showing a pixel electrode according to anotherexemplary embodiment of the present invention;

FIG. 24 is a plan view showing a first substrate according to anotherexemplary embodiment of the present invention;

FIG. 25 is a cross-sectional view showing J-J′ line of FIG. 24;

FIG. 26 is a plan view showing a first substrate according to anotherexemplary embodiment of the present invention;

FIG. 27 is a cross-sectional view showing K-K′ line of FIG. 26;

FIG. 28 is a plan view showing a first substrate according to anotherexemplary embodiment of the present invention; and

FIG. 29 is a cross-sectional view showing L-L′ line of FIG. 28.

BEST MODE FOR CARRYING OUT THE INVENTION

Display Pixel

FIG. 2 is a plan view showing a display pixel according to an exemplaryembodiment of the present invention, and FIG. 3 is a cross-sectionalview showing A-A′ line of FIG. 2.

Referring to FIGS. 2 and 3, the display pixel 110 includes a firsttransparent substrate 111, a channel layer 112, a first insulating layer113, a first signal line 114, a second insulating layer 115, a secondsignal line 116, a third signal line 117 and a pixel electrode 118.

The first transparent substrate 111 includes a glass substrate having ahigh light transmittance.

The channel layer 112 is formed on the first transparent substrate 111.The channel layer 112 comprises polysilicon, and includes a thin film ofa rectangular shape. A laser beam is irradiated onto the amorphoussilicon thin film to form the polysilicon thin film.

The channel layer 112 includes first and second regions 112 a and 112 bimplanted with impurities at a high concentration of a first dose, andthird and fourth regions 112 c and 112 d implanted with impurities at alow concentration of a second dose lower than the first dose.

The first and second regions 112 a and 112 b are formed on both sides ofthe channel region 112. The third and fourth regions 112 c and 112 d areformed adjacent to the first and second regions 112 a and 112 b,respectively. Width of the first and second regions 112 a and 112 b is afirst length L1. Width of the third and fourth regions 112 c and 112 dis a second length L2. A polysilicon region 112 e is formed between thethird and fourth regions 112 c and 112 d, and width of the polysiliconregion 112 e is a third length L3.

The first insulating layer 113 is formed over the first transparentsubstrate 111 having the channel layer 112. The first insulating layer113 includes contact holes 113 a and 113 b through which the first andsecond regions 112 a and 112 b are partially exposed.

The first signal line 114 is formed on the first insulating layer 113,and the first signal line 114 is extended to the first electrode 114 a.The first electrode 114 a is formed on the first insulating layer 113corresponding to the polysilicon region 112 e. A width of the firstelectrode 114 a is substantially equal to the third length L3.

The second insulating layer 115 is formed over the first transparentsubstrate 111 having the first signal line 114. The second insulatinglayer 115 includes first and second contact holes 115 a and 115 bthrough which the first and second regions 112 a and 112 b are partiallyexposed.

The second and third signal lines 116 and 117 are formed on the secondinsulating layer 115.

The second signal line 116 is electrically connected to the first region112 a through the first contact hole 115 a. The third signal line 117 iselectrically connected to the second region 112 b through the secondcontact hole 115 b.

The pixel electrode 118 formed on the second insulating layer 115 isconnected to the third signal line 117. The pixel electrode 118 and thethird signal line 117 are formed with the second insulating layer 115.The pixel electrode 118 includes indium zinc oxide (IZO) that istransparent and conductive. An etchant for patterning the indium zincoxide such as an oxalic acid does not etch the second and third signallines 116 and 117.

The etchant for patterning the indium tin oxide (ITO), however, may etchthe second signal line 116 or the third signal line 117. When the secondsignal line 116 or the third signal line 117 is etched, the secondsignal line 116 or the third signal line 117 may be disconnected or haveincreased resistance.

Therefore, the etchant for patterning the indium zinc oxide prevents thesecond and third signal lines 116 and 117 from being disconnected orhaving increased resistance.

Also, the display pixel is formed without a protecting layer, therebysimplifying manufacturing process.

Method of Manufacturing Display Pixel

FIG. 4 is a plan view showing a channel layer formed on a transparentsubstrate according to another exemplary embodiment of the presentinvention, and FIG. 5 is a cross-sectional view showing B-B′ line ofFIG. 4.

Referring to FIGS. 4 and 5, an amorphous silicon thin film is depositedon a transparent substrate 111, and a laser beam is irradiated onto theamorphous silicon thin film to form the polysilicon thin film. Thepolysilicon thin film is patterned to form a channel layer 112 on thetransparent substrate 111. Preferably, the channel layer 112 includes athin film having a rectangular shape.

A first insulating layer 113 is formed over the transparent substrate111 having the channel layer 112.

FIG. 6 is a plan view showing an LDD structure and a first signal linedisposed corresponding to a channel layer according to an exemplaryembodiment of the present invention, and FIG. 7 is a cross-sectionalview showing C-C′ line of FIG. 6.

Referring to FIGS. 6 and 7, a gate metal thin film 114 b is formed overthe first insulating layer 113. The gate metal thin film 114 b ispatterned to form a first signal line 114.

A heat resistant photoresist thin film is coated over the gate metalthin film 114 b. The heat resistant photoresist thin film is patternedusing the second pattern mask to form an ion mask 114 c disposed over aregion K corresponding to the first signal line.

The gate metal thin film 114 b is patterned using an etchant or etchinggas to form the first signal line 114 and to allow the ion stopper to beunder-cut. An under-cut is formed under the ion mask 114 c. Impuritieshaving different concentrations may be disposed on the channel layer 112because of the under-cut.

FIG. 8 is a cross-sectional view showing a channel layer implanted withimpurities at a high concentration according to an exemplary embodimentof the present invention.

Referring to FIG. 8, the channel layer 112 without the ion mask 114 c isimplanted with impurities at high concentration, and the ion mask 114 cis also implanted with the impurities at a high concentration.

FIG. 9 is a cross-sectional view showing a channel layer implanted withimpurities at a low concentration according to an exemplary embodimentof the present invention.

Referring to FIG. 9, the ion mask 114 c is stripped by a strippingprocess such as an etching process. The channel layer 112 is implantedwith impurities at a low concentration to form third and fourth regions112 c and 112 d. The third and fourth regions are represented byreference numerals “112 c” and “112 d”. Therefore, a first region 112 aand a second region 112 b are disposed adjacent to the third and fourthregions 112 c and 112 d. The channel layer 112 corresponding to thefirst signal line 114 is adjacent to the third and fourth regions 112 cand 112 d.

FIG. 10 is a plan view showing contact holes formed corresponding tofirst and second regions according to an exemplary embodiment of thepresent invention, and FIG. 11 is a cross-sectional view showing D-D′line of FIG. 10.

Referring to FIGS. 10 and 11, the second insulating layer 115 is formedover the transparent substrate 111 having the first signal line 114.

A first contact hole 115 a and a second contact hole 115 b are formed inthe second insulating layer 115 using the third pattern mask. The firstand second regions 112 a and 112 b are partially exposed through thefirst and second contact holes 115 a and 115 b. The first contact hole115 a is opposite to the second contact hole 115 b by interposing thefirst signal line 114 therebetween.

The first and second contact holes 115 a and 115 b of the secondinsulating layer 115 are formed with contact holes 113 a and 113 b ofthe first insulating layer 113.

FIG. 12 is a plan view showing second and third signal line according toan exemplary embodiment, and FIG. 13 is a cross-sectional view showingE-E′ line of FIG. 12.

Referring to FIGS. 12 and 13, a metal thin film is formed on the secondinsulating layer 115. The metal thin film is patterned using the fourthpattern mask to form second and third signal lines 116 and 117.

The second signal line 116 is perpendicular to the first signal line114, and the second signal line 116 is electrically connected to thefirst region 112 a of the channel layer 112 through the first contacthole 115 a.

The third signal line 117 is formed with the second signal line 116. Thethird signal line 117 is parallel with the first signal line 114, andelectrically connected to the second region 112 b of the channel layer112 through the second contact hole 115 b.

Now referring to FIGS. 1 and 2, indium zinc oxide material is formedover the second insulating layer 115 to form an indium zinc oxide layer.The indium zinc oxide layer is patterned using the fourth pattern maskand indium zinc oxide etchant.

The indium zinc oxide etchant may not etch the second and third signallines 116 and 117. Therefore, although etching time for the indium zincoxide layer is no less than a predetermined etching time or thickness ofthe indium zinc oxide layer is no more than a predetermined thickness,the second and third signal lines 116 and 117 may substantially notetched by the indium zinc oxide etchant.

Therefore, the indium zinc oxide is used to form the pixel electrode 118so that a step of forming a protecting layer for protecting the secondand third signal lines 116 and 117 and a step of forming a contact holein the protecting layer may be omitted, thereby simplifyingmanufacturing process of the display pixel.

Display Apparatus

FIG. 14 is a cross-sectional view showing a display apparatus accordingto another exemplary embodiment of the present invention.

Referring to FIG. 14, a display apparatus 200 includes a first substrate210, a second substrate 220 and a liquid crystal layer 230.

The first substrate 210 includes a first transparent substrate 211, achannel layer 212, a first insulating layer 213, a first signal line214, a second insulating Layer 215, a second signal line 216, a thirdsignal line 217, a pixel electrode 218 and an etch stop layer 219.

The first transparent substrate 211 includes a transparent glasssubstrate having high light transmittance.

The channel layer 212 is formed on the first transparent substrate 211.The channel layer 212 includes amorphous silicon thin film having arectangular shape.

The channel layer includes first and second regions 212 a and 212 bimplanted with impurities at a high concentration of a first dose, andthird and fourth regions 212 c and 212 d implanted with impurities at alow concentration of a second dose smaller than the first dose.

The first and second regions 212 a and 212 b are formed on both sides ofthe channel region 212. The third and fourth regions 212 c and 212 d areformed adjacent to the first and second regions 212 a and 212 b,respectively. Width of the first and second regions 212 a and 212 b is afirst length L1. Width of the third and fourth regions 212 c and 212 dis a second length L2. A polysilicon region 212 e is formed between thethird and fourth regions 212 c and 212 d, and width of the polysiliconregion 212 e is a third length L3.

The first insulating layer 213 is formed over the first transparentsubstrate 211 having the channel layer 212. The first insulating layer213 includes contact holes 213 a and 213 b through which the first andsecond regions 212 a and 212 b are partially exposed.

The first signal line 214 is formed on the first insulating layer 213,and the first signal line 214 is extended to the first electrode 214 a.The first electrode 214 a is formed on the first insulating layer 213corresponding to the polysilicon region 212 e. A width of the firstelectrode 214 a is substantially equal to the third length L3.

The second insulating layer 215 is formed over the first transparentsubstrate 211 having the first signal line 214. The second insulatinglayer 215 includes a first contact hole 215 a and a second contact hole215 b, through which the first and second regions 212 a and 212 b arepartially exposed.

The second and third signal lines 216 and 217 are formed on the secondinsulating layer 215.

The second signal line 216 is connected to a second electrode 216 a. Thesecond electrode 216 a is electrically connected to the first region 212a through the first contact hole 215 a. The third signal line 217 isconnected to a third electrode 217 a. The third electrode 217 a iselectrically connected to the second region 212 b through the secondcontact hole 215 b.

The pixel electrode 218 connected to the third signal line 217 is formedon the second insulating layer 215. The pixel electrode 218 includesindium zinc oxide (ITO) that is transparent and conductive.

The etch stop layer 219 is formed over the first transparent substrate211 having the second signal line 216 so as to prevent the second andthird signal lines 216 and 217 from being etched during forming thepixel electrode 218. The etch stop layer 219 includes indium tin oxidelayer.

A common electrode 222 is formed over the second transparent substrate221. A color filter 223 may be disposed between the second transparentsubstrate 221 and the common electrode 222.

Liquid crystal is injected between the first substrate 210 and thesecond substrate 220 to form the liquid crystal layer 230.

FIG. 15 is a plan view showing a channel region formed on a firsttransparent substrate according to another exemplary embodiment, FIG. 16is a cross-sectional view showing F-F′ line of FIG. 15.

Referring to FIGS. 15 and 16, an amorphous silicon thin film 212 f isdeposited on the first transparent substrate 211. The amorphous siliconthin film 212 f is patterned to form the channel layer 212 on the firsttransparent substrate 211. The channel layer 212 has a rectangularshape.

The first insulating layer 213 is formed over the first transparentsubstrate 211 having the channel layer 212.

FIG. 17 is a plan view showing a lightly doned drain (LDD) structure anda first signal line formed corresponding to a channel layer according toanother exemplary embodiment of the present invention, and FIG. 18 is across-sectional view showing G-G′ line of FIG. 17.

Referring to FIGS. 17 and 18, a gate metal thin film is deposited overthe first insulating layer 213. The gate metal thin film is patterned toform the first signal line 214 and the first electrode 214 a.

The first signal line 214 is extended in a first direction. The firstelectrode 214 a is connected to the first signal line 214, and extendedin a second direction perpendicular to the first direction.

An ion mask (not shown) is formed over a region K corresponding to thefirst signal line 214. The first and second regions implanted withimpurities at a high concentration are represented by reference numerals212 a and 212 b. The ion mask is then stripped. The channel layer 212 isimplanted with impurities at a low concentration to form the third andfourth regions. The third and fourth regions implanted with theimpurities at a low concentration are represented by reference numerals“212 c” and “212 d”. Therefore, The first and second regions 212 a and212 b are disposed adjacent to the third and fourth regions 212 c and212 d. The first region 212 a and a portion of the channel region 112corresponding to the first electrode 214 a have the third region 212 ctherebetween, and the second region 212 b and the portion of the channelregion 112 corresponding to the first electrode 214 a have the fourthregion 212 d therebetween.

FIG. 19 is a plan view showing a contact hole formed in a first regionaccording to another exemplary embodiment of the present invention, andFIG. 20 is a cross-sectional view showing H-H′ line of FIG. 19.

Referring to FIGS. 19 and 20, the second insulating layer 215 is formedover the first transparent substrate 211 having the first signal line214 and the first electrode 214 a.

The first and second contact holes 215 a and 215 b are formed in thesecond insulating layer 215. The first and second regions 212 a and 212b are partially exposed through the first and second contact holes 215 aand 215 b. The first contact hole 215 a is opposite to the secondcontact hole 215 b by interposing the first electrode 214 atherebetween.

The contact holes 213 a and 213 b of the first insulating layer 213 areformed together with the first and second contact holes 215 a and 215 bof the second insulating layer 215, respectively.

FIG. 21 is a plan view showing a second and third signal line accordingto another exemplary embodiment of the present invention, and FIG. 22 isa cross-sectional view showing I-I′ line of FIG. 21.

Referring to FIGS. 21 and 22, a metal thin film is deposited over thesecond insulating layer 215. The metal thin film is patterned to formthe second and third signal lines 216 and 217.

The second signal line 216 is extended in the second directionperpendicular to the first signal line 214. The second electrode 216 ais connected to the second signal line 216, and extended in the firstdirection. The second electrode 216 a is electrically connected to thefirst region 212 a of the channel layer 212 through the contact holes215 a and 213 a.

The third signal line 217 is formed with the second signal line 216 andthe second electrode 216 a. The third signal line 217 is parallel withthe first signal line 214. The third signal line 217 is electricallyconnected to the second region 212 b through the contact holes 215 b and213 b.

FIG. 23 is a plan view showing a pixel electrode according to anotherexemplary embodiment of the present invention.

Referring to FIGS. 14 and 23, an indium tin oxide layer is formed overthe second insulating layer 215. The indium tin oxide layer is patternedusing an etchant.

A portion of the indium tin oxide layer is removed so that the indiumtin oxide layer corresponding to the second signal line 216, the secondelectrode 216 a, the third electrode 217 a and the third signal line 217remains.

Therefore, although etching time for the indium tin oxide layer is noless than a predetermined etching time or thickness of the indium tinoxide layer is no more than a predetermined thickness, the second signalline 216, the second electrode 216 a, the third electrode 217 a and thethird signal line 217 may substantially not etched by the etchantbecause of the remaining indium tin oxide layer thereon.

Therefore, the remained indium tin oxide layer corresponding to thesecond signal line 216, the second electrode 216 a, the third electrode217 a and the third signal line 217 prevents the second signal line 216,the second electrode 216 a, the third electrode 27 a and the thirdsignal line 217 from being disconnected or having increased resistance.

The remaining indium tin oxide layer corresponding to the second signalline 216 and the second electrode 216 a is the etch stop layer 219. Theremaining indium tin oxide layer corresponding to the third electrode217 a and the third signal line 217 is the pixel electrode 218.

The common electrode 222 including indium tin oxide layer and the indiumzinc oxide layer is formed on the second transparent substrate 221.

The first substrate 210 is combined with the second substrate 220.Liquid crystal is injected into a space between the first and secondsubstrates 210 and 220.

Therefore, the indium tin oxide layer corresponding to the second signalline 216 and the second electrode 216 a protects the second signal line216 and the second electrode 216 a. Also, the third signal line 217 andthe third electrode 217 a make direct contact with the pixel electrode218 so that the manufacturing process is simplified.

FIG. 24 is a plan view showing a first substrate according to anotherexemplary embodiment of the present invention, and FIG. 25 is across-sectional view showing J-J′ line of FIG. 24.

Referring now in specific detail to FIGS. 24 and 25 in which the samereference numerals denote the same elements in FIGS. 14 to 23, and thusany further detailed descriptions concerning the same elements will beomitted.

Referring to FIGS. 24 and 25, an indium tin oxide layer is depositedover a second insulating layer 215. A portion of the indium tin oxidelayer is etched to form a second electrode part 216 c and a pixelelectrode 218 a. The second electrode part 216 c is electricallyconnected to a first region 212 a through a first contact hole 215 a,and the pixel electrode 218 a is electrically connected to a secondregion 212 b through a second contact hole 215 b.

A metal thin film is formed over a transparent substrate 211 having thesecond electrode part 216 c and the pixel electrode 218 a. The metalthin film is patterned to form a second signal line 216 d. A portion ofthe second signal line 216 d is disposed on the second electrode part216 c.

In general, an etchant for etching a metal thin film may substantiallynot etch indium tin oxide layer.

A common electrode 222 is formed over a second transparent substrate 221to form a second substrate 220. Preferably, a color filter 223 isdisposed between the second transparent substrate 221 and the commonelectrode 222.

A liquid crystal layer 230 is formed between the first substrate 210 andthe second substrate 220 to form the display apparatus 200.

Therefore, the second electrode part 216 c is formed together with thepixel electrode 218 a, and a protecting layer may be omitted to simplifymanufacturing process.

FIG. 26 is a plan view showing a first substrate according to anotherexemplary embodiment of the present invention, and FIG. 27 is across-sectional view showing K-K′ line of FIG. 26.

Referring now in specific detail to FIGS. 26 and 27 in which the samereference numerals denote the same elements in FIGS. 14 to 23, and thusany further detailed descriptions concerning the same elements will beomitted.

Referring to FIGS. 26 and 27, a pixel electrode 218 c is formed on asecond insulating layer 215 having a first contact hole 215 a and asecond contact hole 215 b. The pixel electrode 218 c is separated fromthe first and second contact holes 215 a and 215 b.

A metal thin film is deposited on the second insulating layer 215 havingthe pixel electrode 218 c thereon. The metal thin film is etched byusing an etchant.

Preferably, the etchant may not substantially etch an indium tin oxideof the pixel electrode 218 c.

FIG. 28 is a plan view showing a first substrate according to anotherexemplary embodiment of the present invention, and FIG. 29 is across-sectional view showing L-L′ line of FIG. 28.

The metal thin film is patterned to form a second signal line 216 havinga second electrode 216 a and a third signal line 217 having a thirdelectrode 217 a. The second electrode 216 a is connected to the secondsignal line 216, and electrically connected to a first region 212 athrough the first contact hole 215 a. The third electrode 217 a isconnected to the pixel electrode 218 c, and electrically connected to asecond region 212 b through the second contact hole 215 b.

A common electrode 222 is formed over the second transparent substrate221 to form a second substrate 220. Preferably, a color filter 223 isdisposed between the second transparent substrate 221 and the commonelectrode 222.

A liquid crystal layer 230 is disposed between the first substrate 210and the second substrate 220 to form the display apparatus 200.

Therefore, the pixel electrode 218 c is formed prior to the formation ofthe second and third electrodes 216 a and 217 a, and a protecting layeris omitted, thereby simplifying manufacturing process.

INDUSTRIAL APPLICABILITY

As mentioned above, structure of a display pixel for an LCD apparatusand manufacturing process are simplified to reduce manufacturing costand time.

Also, an indium zinc oxide layer is used as a pixel electrode so that aprotecting layer may be omitted, because the indium zinc oxide layer maynot etch or corrode metal layers.

In addition, an indium tin oxide layer or the indium zinc oxide layer isused as the protecting layer so as to simplify manufacturing process.

Furthermore, a second electrode part is formed together with the pixelelectrode so as to simplify manufacturing process.

Although the exemplary embodiments of the present invention have beendescribed, it is understood that the present invention should not belimited to these exemplary embodiments but various changes andmodifications can be made by one ordinary skilled in the art within thescope of the present invention as hereinafter claimed.

1. A pixel for displays comprising: a channel layer including a channelformed by applying a first voltage; a first signal line applying thefirst voltage to the channel layer; an insulating interlayer insulatingthe first signal line from the channel layer and including a firstcontact hole and a second contact hole through which the channel layeris partially exposed; a second signal line disposed on the insulatinginterlayer and electrically connected to the channel layer through thefirst contact hole; a third signal line disposed on the insulatinginterlayer and electrically connected to the channel layer through thesecond contact hole; and a pixel electrode disposed on the insulatinginterlayer and electrically connected to the third signal line.
 2. Thepixel of claim 1, wherein the pixel electrode comprises indium zincoxide.
 3. The pixel of claim 1, wherein the channel layer furthercomprises a first region and a second region implanted with impuritiesat a relatively higher concentration than the channel layer, and thesecond and third signal lines connected to the first and second regions,respectively.
 4. The pixel of claim 3, wherein the channel layer furthercomprises a third region and a fourth region implanted with impuritiesat a relatively lower concentration than the channel layer, and thethird and fourth regions are disposed adjacent to the first and secondreligions, respectively.
 5. The pixel of claim 1, further comprising aninsulating layer formed on the insulating interlayer.
 6. A method offorming a pixel for displays, the method comprising: forming a channellayer on a substrate using a first pattern mask; forming a first signalline using a second pattern mask; forming a first contact hole and asecond contact hole on an insulating interlayer using a third patternmask, the channel layer being partially exposed through the first andsecond contact holes, and the insulating interlayer insulating the firstsignal line from the channel layer; forming a second signal lineelectrically connected to the channel layer through the first contacthole and a third signal line electrically connected to the channel layerthrough the second contact hole on the insulating interlayer using afourth pattern mask; and forming a pixel electrode electricallyconnected to the third signal line on the insulating interlayer.
 7. Themethod of claim 6, wherein the channel layer is formed by: forming anamorphous silicon layer on the substrate; converting the amorphoussilicon layer into a partially crystallized layer; and patterning thepolysilicon layer by using the first pattern mask.
 8. The method ofclaim 7, further comprising irradiating a laser beam onto the amorphoussilicon layer to form a polysilicon layer.
 9. The method of claim 6,prior to the forming of the first signal line, further comprisingforming the insulating layer disposed on the channel layer.
 10. Themethod of claim 9, wherein the first signal line is formed by: forming ametal layer on the insulating layer; forming an ion stopper on the metallayer corresponding to the channel layer by using the second patternmask; and patterning the metal layer.
 11. The method of claim 10, afterthe forming of the first signal line, further comprising: implantingimpurities into the insulating layer at a first concentration; strippingthe ion stopper; and implanting impurities into the insulating layer ata lower concentration than the first concentration.
 12. The method ofclaim 6, wherein the pixel electrode is formed by depositing indium zincoxide layer over the insulating interlayer.
 13. A display apparatuscomprising: a first substrate including: a first substrate; a channellayer formed on the first transparent substrate; a first signal linehaving a first electrode insulated from the channel layer and disposedat a position corresponding to the channel layer, the first signal linebeing extended in a first direction; a second signal line having asecond electrode connected to the channel layer, the second signal linebeing extended in a second direction; a third signal line having a thirdelectrode connected to the channel layer and insulated from the secondsignal line; a pixel electrode formed over the third signal line; and anetch stop layer disposed over the second signal line; and a secondsubstrate including a second substrate corresponding to the firsttransparent substrate, and a common electrode formed on the secondsubstrate.
 14. The display apparatus of claim 13, wherein the first,second and third signal lines comprise a metal, and wherein the pixelelectrode and the etch stop layer comprise indium tin oxide.
 15. Thedisplay apparatus of claim 13, wherein the first signal line isinsulated from the second and third signal lines by an insulatinginterlayer, and the insulating interlayer includes contact holes throughwhich the second and third signal lines electrically connected to thechannel layer.
 16. A method of manufacturing an LCD apparatus, themethod comprising: forming a first substrate formed by: forming achannel layer on a first substrate; forming a first signal line having afirst electrode insulated from the channel layer and disposed at aposition corresponding to the channel layer; forming a second signalline having a second electrode connected to the channel layer; forming athird signal line having a third electrode insulated from the secondsignal line and connected to the channel layer; and forming a pixelelectrode over the third signal line and an etch stop layer disposedover the second signal line; and forming a common electrode on a secondsubstrate corresponding to the first transparent substrate.
 17. Themethod of claim 16, wherein the pixel electrode and the etch stop layerare formed by: depositing an indium tin oxide layer over the firsttransparent substrate having the second and third signal lines; andpatterning the indium tin oxide layer.
 18. The method of claim 16, afterthe forming of the first signal line, further comprising: forming aninsulating interlayer over the first signal line, the insulating layerhaving a plurality of contact holes.
 19. An LCD apparatus comprising: afirst substrate including: a first transparent substrate; a channellayer formed on the first transparent substrate; a first signal linehaving a first electrode insulated from the channel layer and disposedat a position corresponding to the channel layer; a second electrodeconnected to the channel layer; a second signal line disposed over thesecond electrode; and a pixel electrode connected to the channel layerand insulated from the second electrode; and a second substratecorresponding to the first substrate and a common electrode formed onthe second substrate and corresponding to the pixel electrode.
 20. TheLCD apparatus of claim 19, wherein the first and second signal linescomprise a metal, and wherein the second electrode and pixel electrodecomprise indium tin oxide.
 21. The LCD apparatus of claim 19, whereinthe first signal line is insulated from the second signal line and thepixel electrode by an insulating interlayer, and the insulatinginterlayer includes contact holes through which the second signal lineand the pixel electrode are electrically connected to the channel layer.22. A method of manufacturing an LCD apparatus, the method comprising:forming a first substrate formed by: forming a channel layer on a firstsubstrate; forming a first signal line having a first electrodeinsulated from the channel layer and disposed at a positioncorresponding to the channel layer; forming a second electrode connectedto the channel layer and a pixel electrode connected to the channellayer and insulated from the second electrode; and forming a secondsignal line over the second electrode; and forming a common electrodecorresponding to the pixel electrode on a second substrate.
 23. Themethod of claim 22, wherein the second electrode and the pixel electrodeare formed by: forming an indium tin oxide layer over the firstsubstrate; and patterning the indium tin oxide layer to form the secondelectrode connected to the channel layer and the pixel electrodeconnected to the channel layer.
 24. The method of claim 22, prior to theforming of the second electrode and the pixel electrode, furthercomprising forming an insulating interlayer insulating the first signalline from the channel layer and including contact holes through whichthe first electrode and the pixel electrode are electrically connectedto the channel layer.
 25. An LCD apparatus comprising: a first substrateincluding: a first substrate; a channel layer formed on the firstsubstrate; a first signal line having a first electrode insulated fromthe channel layer and disposed at a position corresponding to thechannel layer; an insulating interlayer insulating the first signal linefrom the channel layer and having a plurality of contact holes; a pixelelectrode formed on the insulating interlayer; a second signal lineincluding a second electrode connected to the channel layer; a thirdelectrode connected to the channel layer and insulated from the secondsignal line; and a third signal line disposed on the pixel electrode andelectrically connected to the pixel electrode; and a second substratecorresponding to the first substrate and a common electrode formed onthe second substrate.
 26. The LCD apparatus of claim 25, wherein thesecond and third signal lines comprise a metal, and wherein the pixelelectrode comprises indium tin oxide.
 27. A method of manufacturing anLCD apparatus comprising: forming a first substrate is formed by:forming a channel layer on a first substrate; forming a first signalline including a first electrode insulated from the channel layer anddisposed at a position corresponding to the channel layer; forming aninsulating interlayer insulating the first signal line from the channellayer and including a plurality of openings; forming a pixel electrodeon the insulating interlayer; and forming a second signal line includinga second electrode connected to the channel layer, and a third signalline including a third electrode connected to the channel layer and thepixel electrode and insulated from the second signal line; and forming acommon electrode corresponding to the pixel electrode on a secondsubstrate.